Secured interaction between embedded devices is becoming ubiquitous in every platform in which it is implemented. Trusted environment involves authentication or identification by another party and/or secure transition of private information after the data was encrypted by a safe algorithm. The vast majority of secured interaction requires storing secured key inside or at the vicinity of the secured hardware. For example, in the case of mobile devices in the medium to low level security hazards, the secret key will be stored by external nonvolatile memory. Beside the cost and power drawbacks of this approach it is extremely vulnerable to security attacks.
Physical unclonable functions (PUFs) are used for authentication, identification and secret key storage with superior performance, lower cost and above all high resistance to reverse engineering or any kind of tampering by a hostile attacker. The PUFs rely on intrinsic undetectable manufacturing variations in the CMOS process. An example of an SRAM PUF scheme is described in the inventor's U.S. patent application Ser. No. 15/694,809, which is incorporated herein by reference.
The known intrinsic silicon PUF constructions can be classified into several basic classes based on the electrical attributes that determine the fingerprint binary output. The first major class relies on the random variations of cumulative delay on a digital circuit. This class includes the arbiter PUF, the ring oscillator PUF and glitch PUF. The second class of silicon PUF constructions uses random mismatch, in bistable memory loop elements. When device is powered up the loop is in a metastable state where any mismatch between the CMOS transistor comprising the loop will yield a probable resolution toward “1” or “0”. This group includes the SRAM PUF, Mecca PUF and any other NOR/NAND latch or flip-flop based PUF.
These two classes of “digital” PUFs have very large PVT (process voltage temperature) and noise variations, leading to a constrained temperature specification for PUF operation (20-50° C.) and various error-correction-codes (ECC) and/or encumbering compensation hardware.
A prior art PUF that utilizes the trip point of an inverter is shown in FIG. 1. In this PUF, a first inverter i1 is biased with its output connected to its input, such that the voltage will be Vm or Vref, the trip point of the inverter. The output of inverter i1 is input into a second inverter i2. The mismatches between the two trip points determine if the output will be a logical “1” or “0”. If there is a sufficient mismatch, the PUF will always yield the same logical value, meaning the output will always be an unambiguous logical “1” or “0”. However, if the mismatch is small, then the noise in the devices (thermal noise) or environmental noise will dominate, and the PUF can alternate between logical values, and hence be unstable.